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 VEGA Ultrafast ConvertersMicram VEGA DAC/ADC chips are the only products of their kind. VEGA enables the only practical, running 100G data transmission development environment available today. VEGA give 100GbE developers the power to make immediate, significant progress by providing an off-the-shelf, full-bandwidth 100G environment - without a custom chip run. VEGA is open, scalable and easily adapted to any application-specific requirements.Unlike other DAC/ADC product architectures which force early design decisions that are costly and time-consuming to change, VEGA enables developers to rapidly prototype their ideas, test them and make revisions on the fly. With VEGA, developers can quickly assemble a highly productive, real-time 100G development system and start creating system-level product designs immediately. DAC I and DAC II Following the success of our original digital to analog converter chip, the sold-out DAC25, Micram now offers a family of second generation VEGA DACs offering developers even more performance and design flexibility: VEGA DAC I with samopling rates up to 25GS/s, and VEGA DAC II which achieves sampling rates as high as 34 GS/s. Incorporating everything we've learned from the success of VEGA DAC25, our latest chips deliver extraordinary performance that meets the capabilities of the latest generation of FPGAs, including the Xilinx Virtex5 and Altera Stratix IV. For more information on the DAC I and II click here. ADC 30 The ground-breaking VEGA ADC 30 is a 30 GS/s, 6 bit analog to digital converter with >20 GHZ bandwidth. Even greater performance can be achieved with two VEGA ADC 30 evaluation boards can be configured in a multi-channel interleave mode, enabling two-channel 60 GS/s @ >20 GHz sampling rates. The Low Risk Path for 100GbE Development The competitive advantage available to developers using VEGA is potentially game-changing. Already up to four VEGA chips can be synchronized for an interleave mode using the CD15 versatile clock distribution module. See also the application note in the Literature section below. VEGA converters will be delivering their unbeatable level of performance in a single BGA package that will interface with standard or custom specific DSP or FPGA data processors and provide a remarkably flexible and efficient core for system-level 100GbE products. There is no clearer path to the 100GbE market available today. For more on the VEGA path to 100GbE leadership, please read our brief VEGA white paper here. DAC I and DAC II We are now offering two versions of our second-generation VEGA DAC: DAC I with sampling rates up to 25 GS/s, and DAC II which achieves rates as high as 34GS/s. The VEGA DAC digital-to-analog signal converter family, with a sample rate of up to 34GS/s at 20Ghz bandwidth. Incorporating everything we've learned from the success of the sold-out VEGA DAC25, our latest chip delivers extraordinary performance that meets - and even exceeds - the capabilities of the latest generation of FPGAs, including the Xilinx Virtex5 and Altera Stratix IV. Up to 4 DAC chips can be synchronized with our CD15 timing module for even greater performance potential.  The scalable open architecture offers a high degree of flexibility in order to adopt the rapidly changing requirements in future high-speed converter applications. Having a physical resolution of 6 bits, we measured an ENOB of >4.5bit at 30 GS/s with a sinusoidal differential signal of 14 GHz. In the high-speed front end, the VEGA architecture allows a tradeoff between conversion rate, resolution and power consumption for optimum tailored application specific performance. For massive signal and data processing in digital domain, the architecture offers a parallel interface to either commercially available high-speed FPGAs or to a separate custom specific realization in off the shelf standard CMOS technology. This allows to keep the high performance analog front end, and to implement the latest developments in data/signal processing by updates on the CMOS part only. The chip with 6 bit resolution is available now. It comes along with an application board that offers two different input interfaces. A low speed USB or RS232 interface to a PC allows configuring and loading up repeatable test-patterns to the converter. For continuous at-speed input, a high-speed interface offers 24 differential inputs for drive with commercially available FPGAs, e.g. Xilinx VIRTEX-5 or Altera Stratix V. The converter is well suited for direct digital synthesis of ultra high-speed arbitrary waveforms e.g. for advanced 100 Gbit Ethernet transmission schemes. The data transfer from FPGA/CMOS is carried via 24 serial lines (LVDS) running at fsample/4, i.e. 8.5Gb/s for 34GS/s (6 bit * 1:4 Mux ==> 24 signals). The FPGA interface carries raw data only, i.e. no line coding etc. but optionally can be PRBS scrambled. In addition, a register bus (LVTTL, serial) can be used to configure the D/A converter. The Evaluation Board (shown here) comes with a microcontroller and a software application to control operation modes. It is able to check the synchronization of the 24 FPGA channels. The 24 differential serial data lines are connected with the chip carrier module via high density Samtec RF connectors. All other DC signals are also carried through Samtec connectors. Clock input and DAC output are interfaced by K-connectors. Specification Data
* se = single-ended, fs = full-scale (e.g. 6b000000 ? 6b111111) For more on the VEGA path to 100GbE leadership, please download the VEGA DAC I and DAC II data sheet here. VEGA ADC 30 Key Data(product available in 2010) The ADC 30 is designed for 30GS/s to show the inherent performance and functional capability of the VEGA modular approach. It consists of an input-amplifier, track-and-hold circuit, ADC-core and output logic. The converter has a bandwidth of 20GHz, which shows up when operating two ADCs in interleave mode to provide 60GS/s @ 20 GHz. Like DAC 25, the first chips will be available with an evaluation board. The ADC chip is mounted to the PCB board on a chip-carrier (shown here) which allows easy swapping of ADC chips to different (customer) boards.  The conversion will be interleaved, there will be several blocks sharing the conversion operation. Results are processed in a logic block and de-mulitplexed for further processing by external CMOS FPGA chips. The RF-Clock is fed directly into the A/D converter and provides a reference clock to the FPGA. Depending on customer needs there is an option to include a VCO on the chip in later versions. Data-transfer to FPGA will be via 24 serial lines (LVDS or PCML, differential) running at fsample/4, e.g. 7.5Gb/s for 30GS/s (6 bit * 1:4 Mux --> 24 signals). The 24 differential serial data lines are connected with the chip carrier module via high density Samtec RF connectors. All other DC signals are also carried through Samtec connectors. Clock input and signal input are interfaced by K-connectors. In addition a register bus (LVTTL, serial) is used to configure and calibrate the A/D converter. Dedicated on-chip circuitry will support for easy calibration. The high-speed interface will carry raw data only, without line coding (except scrambling) or framing. To compensate for skew on PCB as well as to align input stages in the FPGA, the A/D converter can be switched into a dedicated synchronization mode. Since some FPGA require a certain amount of data edges on the input channels to stay synchronized, the data transmitted to the FPGA can be optionally PRBS scrambled to enforce transitions even while the ADC-input is static.
Target Data
For more on the VEGA path to 100GbE leadership, please download the VEGA ADC30 perliminary datasheet here.
VEGA Evaluation BoardThe scalable open architecture offers a high degree of flexibility in order to adopt the rapidly changing requirements in future high-speed converter applications. A single VEGA Evlauation board provides for either DAC I, DAC II or ADC30 modules. The firmware recognizes the type of module and provides an easy adminsitration and setup interface via USB serial connections to any PC for easy lab usage. All high-speed signals are accessible via RF connectors - a purpose-built cable-set to connect FPGA boards is available. For sycnhronization a separate FPGA interface is provided as well as a connector for the CD15 clock distribution module to operate up to 4 VEGA boards in a synchronized mode. For massive signal and data processing in digital domain, the architecture offers a parallel interface to either commercially available high-speed FPGAs or to a separate custom specific realization in off the shelf standard CMOS technology.  This allows to keep the high performance analog front end, and to implement the latest developments in data/signal processing by updates on the CMOS part only. The data transfer from FPGA/CMOS is carried via 24 serial lines (LVDS) running at fsample/4, i.e. 6.25Gb/s for 25GS/s (6 bit * 1:4 Mux ==> 24 signals). The FPGA interface can be scrambled. A synchronization circuit on the VEGAADC or DAC can be used to align the skews of the channels. In addition, a register bus (LVTTL, serial) can be used to configure the VEGA converter. The Evaluation Board (shown here) comes with a microcontroller and a software application to control operation modes. It is able to establish and check the synchronization of the 24 FPGA channels. The 24 differential serial data lines are connected with the chip carrier module via high density Samtec RF connectors. All other DC signals are also carried through Samtec connectors. Clock input and DAC output are interfaced by K-connectors. LiteratureDownload the VEGA Whitepaper on Signal Converters and find the VEGA datasheets below.
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