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DAC I and DAC II We are now offering two versions of our second-generation VEGA DAC: DAC I with sampling rates up to 25 GS/s, and DAC II which achieves rates as high as 34GS/s. The VEGA DAC digital-to-analog signal converter family, with a sample rate of up to 34GS/s at 20Ghz bandwidth. Incorporating everything we've learned from the success of the sold-out VEGA DAC25, our latest chip delivers extraordinary performance that meets - and even exceeds - the capabilities of the latest generation of FPGAs, including the Xilinx Virtex5 and Altera Stratix IV. Up to 4 DAC chips can be synchronized with our CD15 timing module for even greater performance potential.  The scalable open architecture offers a high degree of flexibility in order to adopt the rapidly changing requirements in future high-speed converter applications. Having a physical resolution of 6 bits, we measured an ENOB of >4.5bit at 30 GS/s with a sinusoidal differential signal of 14 GHz. In the high-speed front end, the VEGA architecture allows a tradeoff between conversion rate, resolution and power consumption for optimum tailored application specific performance. For massive signal and data processing in digital domain, the architecture offers a parallel interface to either commercially available high-speed FPGAs or to a separate custom specific realization in off the shelf standard CMOS technology. This allows to keep the high performance analog front end, and to implement the latest developments in data/signal processing by updates on the CMOS part only. The chip with 6 bit resolution is available now. It comes along with an application board that offers two different input interfaces. A low speed USB or RS232 interface to a PC allows configuring and loading up repeatable test-patterns to the converter. For continuous at-speed input, a high-speed interface offers 24 differential inputs for drive with commercially available FPGAs, e.g. Xilinx VIRTEX-5 or Altera Stratix V. The converter is well suited for direct digital synthesis of ultra high-speed arbitrary waveforms e.g. for advanced 100 Gbit Ethernet transmission schemes. The data transfer from FPGA/CMOS is carried via 24 serial lines (LVDS) running at fsample/4, i.e. 8.5Gb/s for 34GS/s (6 bit * 1:4 Mux ==> 24 signals). The FPGA interface carries raw data only, i.e. no line coding etc. but optionally can be PRBS scrambled. In addition, a register bus (LVTTL, serial) can be used to configure the D/A converter. The Evaluation Board (shown here) comes with a microcontroller and a software application to control operation modes. It is able to check the synchronization of the 24 FPGA channels. The 24 differential serial data lines are connected with the chip carrier module via high density Samtec RF connectors. All other DC signals are also carried through Samtec connectors. Clock input and DAC output are interfaced by K-connectors. Specification Data
* se = single-ended, fs = full-scale (e.g. 6b000000 ? 6b111111) For more on the VEGA path to 100GbE leadership, please download the VEGA DAC I and DAC II data sheet here. |
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