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VEGA ADC 30 Key Data(product available in 2010) The ADC 30 is designed for 30GS/s to show the inherent performance and functional capability of the VEGA modular approach. It consists of an input-amplifier, track-and-hold circuit, ADC-core and output logic. The converter has a bandwidth of 20GHz, which shows up when operating two ADCs in interleave mode to provide 60GS/s @ 20 GHz. Like DAC 25, the first chips will be available with an evaluation board. The ADC chip is mounted to the PCB board on a chip-carrier (shown here) which allows easy swapping of ADC chips to different (customer) boards.  The conversion will be interleaved, there will be several blocks sharing the conversion operation. Results are processed in a logic block and de-mulitplexed for further processing by external CMOS FPGA chips. The RF-Clock is fed directly into the A/D converter and provides a reference clock to the FPGA. Depending on customer needs there is an option to include a VCO on the chip in later versions. Data-transfer to FPGA will be via 24 serial lines (LVDS or PCML, differential) running at fsample/4, e.g. 7.5Gb/s for 30GS/s (6 bit * 1:4 Mux --> 24 signals). The 24 differential serial data lines are connected with the chip carrier module via high density Samtec RF connectors. All other DC signals are also carried through Samtec connectors. Clock input and signal input are interfaced by K-connectors. In addition a register bus (LVTTL, serial) is used to configure and calibrate the A/D converter. Dedicated on-chip circuitry will support for easy calibration. The high-speed interface will carry raw data only, without line coding (except scrambling) or framing. To compensate for skew on PCB as well as to align input stages in the FPGA, the A/D converter can be switched into a dedicated synchronization mode. Since some FPGA require a certain amount of data edges on the input channels to stay synchronized, the data transmitted to the FPGA can be optionally PRBS scrambled to enforce transitions even while the ADC-input is static.
Target Data
For more on the VEGA path to 100GbE leadership, please download the VEGA ADC30 perliminary datasheet here.
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