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VEGA Evaluation BoardThe scalable open architecture offers a high degree of flexibility in order to adopt the rapidly changing requirements in future high-speed converter applications. A single VEGA Evlauation board provides for either DAC I, DAC II or ADC30 modules. The firmware recognizes the type of module and provides an easy adminsitration and setup interface via USB serial connections to any PC for easy lab usage. All high-speed signals are accessible via RF connectors - a purpose-built cable-set to connect FPGA boards is available. For sycnhronization a separate FPGA interface is provided as well as a connector for the CD15 clock distribution module to operate up to 4 VEGA boards in a synchronized mode. For massive signal and data processing in digital domain, the architecture offers a parallel interface to either commercially available high-speed FPGAs or to a separate custom specific realization in off the shelf standard CMOS technology.  This allows to keep the high performance analog front end, and to implement the latest developments in data/signal processing by updates on the CMOS part only. The data transfer from FPGA/CMOS is carried via 24 serial lines (LVDS) running at fsample/4, i.e. 6.25Gb/s for 25GS/s (6 bit * 1:4 Mux ==> 24 signals). The FPGA interface can be scrambled. A synchronization circuit on the VEGAADC or DAC can be used to align the skews of the channels. In addition, a register bus (LVTTL, serial) can be used to configure the VEGA converter. The Evaluation Board (shown here) comes with a microcontroller and a software application to control operation modes. It is able to establish and check the synchronization of the 24 FPGA channels. The 24 differential serial data lines are connected with the chip carrier module via high density Samtec RF connectors. All other DC signals are also carried through Samtec connectors. Clock input and DAC output are interfaced by K-connectors. |
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